A Bit-Plane Decomposition Matrix-Based VLSI Integer Transform Architecture for HEVC

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 64; no. 3; pp. 349 - 353
• Main Authors: Qi, Honggang, Huang, Qingming, Gao, Wen
• Format: Journal Article
• Language: English
• Published: IEEE 01.03.2017
• Subjects: Adders; Bit-plane matrix; Delays; Discrete cosine transforms; High Efficiency Video Coding (HEVC); integer transform; Matrix decomposition; Sparse matrices; ultra high definition (HD); Very large scale integration; very-large-scale integrated (VLSI) architecture
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2016.2576061

In this brief, a new very-large-scale integrated (VLSI) integer transform architecture is proposed for the High Efficiency Video Coding (HEVC) encoder. The architecture is designed based on the signed bit-plane transform (SBT) matrices, which are derived from the bit-plane decompositions of the integer transform matrices in HEVC. Mathematically, an integer transform matrix can be equally expressed by the binary weighted sum of several SBT matrices that are only composed of binary 0 or ±1. The SBT matrices are very simple and have lower bit width than the original integer transform in the form. The SBT matrices are also sparse and there are many zero elements. The sparse characteristic of SBT matrices is very helpful for saving the addition operators of SBT. In the proposed architecture, instead of the original integer transform in high bit width, the video data can be respectively transformed with the SBT matrices in lower bit width. As a result, the delay of the transform unit circuit can be significantly reduced with the proposed SBT. Moreover, exploiting the redundant element characteristic of SBT matrices, in which the elements are 0 or ±1, the adder reuse strategy is proposed for our transform architecture, which can save the circuit area efficiently. The simulation results show that by employing the proposed strategies the VLSI transform architecture can be synthesized in a proper area with a high working frequency and low latency. The architecture can support all HEVC encoders coding ultra high-definition video sequences in real time.