A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements

We propose a cache architecture using a 7T/14T SRAM (Fujiwara et al., 2009) and a control mechanism for reliability enhancements. Our control mechanism differs from conventional dynamic voltage-frequency scaling (DVFS) methods in that it considers not only the cycles per instruction behaviors but al...

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Bibliographic Details
Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 25; no. 3; pp. 820 - 832
Main Authors Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Wu, Allen C.-H, TingTing Hwang
Format Journal Article
LanguageEnglish
Published IEEE 01.03.2017
Subjects
7T/14T SRAM
cache
Computer architecture
dynamic voltage-frequency scaling (DVFS)
Error correction codes
Reliability
SRAM cells
Switches
Voltage control
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Summary:We propose a cache architecture using a 7T/14T SRAM (Fujiwara et al., 2009) and a control mechanism for reliability enhancements. Our control mechanism differs from conventional dynamic voltage-frequency scaling (DVFS) methods in that it considers not only the cycles per instruction behaviors but also the cache utilization. To measure cache utilization, a novel metric is proposed. The experimental results show that our proposed method achieves 1000 times less bit-error occurrences compared with conventional DVFS methods under the ultralow-voltage operation. Moreover, the results indicate that our proposed method surprisingly not only incurs no performance and energy overheads but also achieves on average a 2.10% performance improvement and a 6.66% energy reduction compared with conventional DVFS methods.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2016.2614993