Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 29; no. 1; pp. 2 - 13
• Main Authors: Meterelliyoz, Mesut, Kulkarni, Jaydeep P., Roy, Kaushik
• Format: Journal Article
• Language: English
• Published: IEEE 01.01.2010
• Subjects: 6-T SRAM; 8-T SRAM; Cache memory; Circuit noise; Circuit stability; compact thermal models; DRAM chips; eDRAM; Logic; Performance analysis; Random access memory; robustness; SRAM chips; stability; Temperature dependence; Temperature sensors; thermal analysis; thermal aware design methodology
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2009.2035535

In scaled technologies, cache memories which are traditionally known as "cold" sections of the chip are expected to occupy a larger die area. Hence, different sections of a cache memory may experience different temperature profiles depending on their proximity to the active logic units such as the execution unit. In this paper, we performed thermal analysis of cache memories under the influence of hot-spots. In particular, 6-transistor (T) static random access memory (SRAM), 8-T SRAM, and embedded dynamic random access memory (eDRAM) cache memories were investigated. Thermal maps of the entire caches were generated using hierarchical compact thermal models while solving the leakage and temperature self-consistently. The 6-T and the 8-T SRAM bitcells were investigated in terms of stability, noise immunity, and performance under temperature variations for various technology nodes. The 3-T micro sense amplifier used in eDRAM cache memories was investigated for its robustness. Thermal-aware circuit design techniques were explored to improve cache stability under thermal gradients. Results show that, for all cache memories, spatial temperature variations have to be considered to achieve the optimal memory design.