Low Latency GF(2^) Polynomial Basis Multiplier

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 58; no. 5; pp. 935 - 946
• Main Author: Imana, José Luis
• Format: Journal Article
• Language: English
• Published: IEEE 01.05.2011
• Subjects: Clocks; Complexity theory; Computer architecture; Elliptic curve cryptography; Finite fields; implementation; Matrix decomposition; multiplication; polynomial basis; Polynomials; VLSI
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2010.2089553

Finite field GF (2 m ) arithmetic is becoming increasingly important for a variety of different applications including cryptography, coding theory and computer algebra. Among finite field arithmetic operations, GF (2 m ) multiplication is of special interest because it is considered the most important building block. This contribution describes a new low latency parallel-in/parallel-out sequential polynomial basis multiplier over GF (2 m ). For irreducible GF (2 m ) generating polynomials f ( x )= xm + xkt + xk t -1+⋯+ xk 1 +1 with m ≥ 2 k t -1, the proposed multiplier has a theoretical latency of 2 kt +1 cycles . This latency is the lowest one found in the literature for GF (2 m ) multipliers. Furthermore, the condition m ≥ 2 kt -1 is specially important because the five binary irreducible polynomials recommended by NIST for elliptic curve cryptography (ECC) implementation verify this condition.