Cache-processor coupling: a fast and wide on-chip data cache design
This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address h...
Saved in:
Published in | IEEE journal of solid-state circuits Vol. 30; no. 4; pp. 375 - 382 |
---|---|
Main Authors | , , , |
Format | Journal Article Conference Proceeding |
Language | English |
Published |
New York, NY
IEEE
01.04.1995
Institute of Electrical and Electronics Engineers |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 /spl mu/m CMOS design rule.< > |
---|---|
AbstractList | This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 mum CMOS design rule This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 /spl mu/m CMOS design rule.< > |
Author | Motomura, M. Yamada, H. Inoue, T. Konagaya, A. |
Author_xml | – sequence: 1 givenname: M. surname: Motomura fullname: Motomura, M. organization: Syst. ULSI Res. Lab., Microelectron. Res. Lab., Kanagawa, Japan – sequence: 2 givenname: T. surname: Inoue fullname: Inoue, T. organization: Syst. ULSI Res. Lab., Microelectron. Res. Lab., Kanagawa, Japan – sequence: 3 givenname: H. surname: Yamada fullname: Yamada, H. organization: Syst. ULSI Res. Lab., Microelectron. Res. Lab., Kanagawa, Japan – sequence: 4 givenname: A. surname: Konagaya fullname: Konagaya, A. |
BackLink | http://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=3536932$$DView record in Pascal Francis |
BookMark | eNpFkM1Lw0AQxRepYK2CZ097EPGSut9NvEnwCwpeFLyF6Wa2XUk3cTdF_O9NSVHmMAzzm_eGd0omoQ1IyAVnc85ZcavmcqELbY7IlGudZ3whPyZkyhjPs0IwdkJOU_ocRqVyPiVlCXaDWRdbiym1kdp21zU-rO8oUAeppxBq-u1rpG3I7MZ3tIYeqN2f0RqTX4czcuygSXh-6DPy_vjwVj5ny9enl_J-mVlhdJ8BU7YGx_PVUNoVDqyw1plaGqiRCWW5VrkzRQEIThvtBNMrp_gClZFayBm5HnWHb792mPpq65PFpoGA7S5VIhdMDBkM4M0I2timFNFVXfRbiD8VZ9U-pUpVY0oDenXQhGShcRGC9emPl1qaQu6tL0fMI-L_dtT4Be3Ob8k |
CODEN | IJSCBC |
Cites_doi | 10.1109/40.216748 10.1109/JSSC.1987.1052705 10.1109/4.52161 |
ContentType | Journal Article Conference Proceeding |
Copyright | 1995 INIST-CNRS |
Copyright_xml | – notice: 1995 INIST-CNRS |
DBID | IQODW AAYXX CITATION 7SP 8FD L7M |
DOI | 10.1109/4.375956 |
DatabaseName | Pascal-Francis CrossRef Electronics & Communications Abstracts Technology Research Database Advanced Technologies Database with Aerospace |
DatabaseTitle | CrossRef Technology Research Database Advanced Technologies Database with Aerospace Electronics & Communications Abstracts |
DatabaseTitleList | Technology Research Database |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Engineering Applied Sciences |
EISSN | 1558-173X |
EndPage | 382 |
ExternalDocumentID | 10_1109_4_375956 3536932 375956 |
GroupedDBID | -~X .DC 0R~ 29I 3EH 4.4 41~ 5GY 5VS 6IK 97E AAJGR AASAJ ABQJQ ABVLG ACGFS ACIWK ACNCT AENEX AETIX AI. AIBXA AKJIK ALLEH ALMA_UNASSIGNED_HOLDINGS ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 EBS EJD F5P HZ~ H~9 IAAWW IBMZZ ICLAB IFIPE IFJZH IPLJI JAVBF LAI M43 O9- OCL P2P PZZ RIA RIE RIG RNS TAE TN5 UKR VH1 XFK IQODW AAYXX CITATION 7SP 8FD L7M |
ID | FETCH-LOGICAL-c265t-a04cdaf18b8b85f9fac2ccf6d36ade024c1548f699aeaf565f205bf417e463523 |
IEDL.DBID | RIE |
ISSN | 0018-9200 |
IngestDate | Fri Aug 16 09:13:19 EDT 2024 Fri Aug 23 03:21:24 EDT 2024 Sun Oct 22 16:09:10 EDT 2023 Wed Jun 26 19:25:56 EDT 2024 |
IsPeerReviewed | true |
IsScholarly | true |
Issue | 4 |
Keywords | Waveform System architecture Integration VLSI circuit Parallel configuration Function block diagram Circuit design Pipeline processor Cache memory Theoretical study Chip Addressing Operation study Energy dissipation Complementary MOS technology High speed Coupling Microprocessor Timing |
Language | English |
License | CC BY 4.0 |
LinkModel | DirectLink |
MeetingName | 1994 VLSI circuits symposium |
MergedId | FETCHMERGED-LOGICAL-c265t-a04cdaf18b8b85f9fac2ccf6d36ade024c1548f699aeaf565f205bf417e463523 |
Notes | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
PQID | 28202109 |
PQPubID | 23500 |
PageCount | 8 |
ParticipantIDs | crossref_primary_10_1109_4_375956 pascalfrancis_primary_3536932 ieee_primary_375956 proquest_miscellaneous_28202109 |
PublicationCentury | 1900 |
PublicationDate | 1995-04-01 |
PublicationDateYYYYMMDD | 1995-04-01 |
PublicationDate_xml | – month: 04 year: 1995 text: 1995-04-01 day: 01 |
PublicationDecade | 1990 |
PublicationPlace | New York, NY |
PublicationPlace_xml | – name: New York, NY |
PublicationTitle | IEEE journal of solid-state circuits |
PublicationTitleAbbrev | JSSC |
PublicationYear | 1995 |
Publisher | IEEE Institute of Electrical and Electronics Engineers |
Publisher_xml | – name: IEEE – name: Institute of Electrical and Electronics Engineers |
References | ref7 kane (ref2) 1992 hennessy (ref1) 1990 ref4 ref3 suzuki (ref6) 1993 matsui (ref5) 1994 |
References_xml | – start-page: 12.4.1 year: 1993 ident: ref6 article-title: A 2.4-ns, 16-b, 0.5-?m CMOS arithmetic logic unit for microprogrammable video signal processor LSIs publication-title: Proc IEEE 1993 CICC contributor: fullname: suzuki – ident: ref7 doi: 10.1109/40.216748 – ident: ref3 doi: 10.1109/JSSC.1987.1052705 – year: 1990 ident: ref1 publication-title: Computer Architecture A Quantitative Approach contributor: fullname: hennessy – year: 1994 ident: ref5 article-title: 200 MHz video compression macrocells using low-swing differential logic publication-title: IEEE ISSCC Dig Tech Papers contributor: fullname: matsui – year: 1992 ident: ref2 publication-title: MIPS RISC Architecture contributor: fullname: kane – ident: ref4 doi: 10.1109/4.52161 |
SSID | ssj0014481 |
Score | 1.520146 |
Snippet | This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures... |
SourceID | proquest crossref pascalfrancis ieee |
SourceType | Aggregation Database Index Database Publisher |
StartPage | 375 |
SubjectTerms | Applied sciences Bandwidth Clocks Coupling circuits Delay Design. Technologies. Operation analysis. Testing Electronics Energy consumption Exact sciences and technology Integrated circuits Laboratories Microprocessor chips Parallel architectures Process design Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon |
Title | Cache-processor coupling: a fast and wide on-chip data cache design |
URI | https://ieeexplore.ieee.org/document/375956 https://search.proquest.com/docview/28202109 |
Volume | 30 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1LS8QwEA7qSQ8-VsX1GcFrapqm2Y03WZRF0JOCt5LmoSK0i9si-OudJN3VVQ_SS2lIKZOk-SYz3zcInUmXcWe0I7mhhsBKFKRk1hBBneQDxZjKPRv59k6MH_jNY_7Y6WwHLoy1NiSf2cTfhli-qXXrj8rOs0EOcH4ZLQ8pi1StecAAvIxYHC-F9Qsj3-nMplSe8yT2W9h5QikVnwippmALF4tY_Pofh03meiOyt6dBm9DnlrwmbVMm-uOHcuM_v38TrXdgE1_G2bGFlmzVQ2vfJAi30WjkFZ3JJPIF6jes69aTdJ8usMJOTRusKoPfX4zFdUX088sE-6RSrH03bEL-xw56uL66H41JV1iBaCbyhijKtVEuHZZw5U46pZnWTphMKGNh19bekXFCSmWVA8jnGM1Lx9OB5QBQWLaLVqq6snsI80xYY0o6tAa6GDOUVGclSwEXAFSgZR-dzoxeTKJ-RhH8DioLXkSD9FHP22rePnt6tDA4X815JgB19tHJbLAKWBI-zqEqW7fTArxI78nK_T_fe4BWIy3dZ98copXmrbVHACya8jhMqU_a58yJ |
link.rule.ids | 310,311,315,786,790,795,796,802,23958,23959,25170,27957,27958,55109 |
linkProvider | IEEE |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3JTsMwELWgHIADSwFRoNRIXN26iePW3FBFVdYTSL1FjhdASElFEyHx9YzttqwHlEsUx5EytjNv4nlvEDoVNmZWK0sSTTWBlchJFhlNOLWC9WQUycSxkW_v-OiBXY2T8Uxn23NhjDE--cy03anfy9eFqtyvsk7cSwDOL6MVcPNUBLLWYssA4oxQHq8LKxjGfqY0Czd2WDv0_OZ7fDEVlwopp2ANG8pY_Poiezcz3Az87alXJ3TZJS_tqsza6v2HduM_32ALbczgJj4P82MbLZm8jta_iBDuoMHAaTqTSWAMFK9YFZWj6T6eYYmtnJZY5hq_PWuDi5yop-cJdmmlWLluWPsMkF30MLy4H4zIrLQCURFPSiIpU1rabj-DI7HCShUpZbmOudQG_LZyoYzlQkgjLYA-G9Eks6zbMwwgShTvoVpe5GYfYRZzo3VG-0ZDF637gqo4i7qADAAs0KyBTuZGTydBQSP1kQcVKUuDQRqo7my1aJ9fbX4bnM_mJOaAOxuoNR-sFBaF2-mQuSmqaQpxpItlxcGfz22h1dH97U16c3l3fYjWAknd5eIcoVr5WpkmwIwyO_bT6wPPBc_f |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=proceeding&rft.title=IEEE+journal+of+solid-state+circuits&rft.atitle=Cache-processor+coupling%3A+a+fast+and+wide+on-chip+data+cache+design&rft.au=MOTOMURA%2C+M&rft.au=INOUE%2C+T&rft.au=YAMADA%2C+H&rft.au=KONAGAYA%2C+A&rft.date=1995-04-01&rft.pub=Institute+of+Electrical+and+Electronics+Engineers&rft.issn=0018-9200&rft.eissn=1558-173X&rft.volume=30&rft.issue=4&rft.spage=375&rft.epage=382&rft_id=info:doi/10.1109%2F4.375956&rft.externalDBID=n%2Fa&rft.externalDocID=3536932 |
thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0018-9200&client=summon |
thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0018-9200&client=summon |
thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0018-9200&client=summon |