Cache-processor coupling: a fast and wide on-chip data cache design

• Published in: IEEE journal of solid-state circuits Vol. 30; no. 4; pp. 375 - 382
• Main Authors: Motomura, M., Inoue, T., Yamada, H., Konagaya, A.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.04.1995; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Bandwidth; Clocks; Coupling circuits; Delay; Design. Technologies. Operation analysis. Testing; Electronics; Energy consumption; Exact sciences and technology; Integrated circuits; Laboratories; Microprocessor chips; Parallel architectures; Process design; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Waveform; System architecture; Integration; VLSI circuit; Parallel configuration; Function block diagram; Circuit design; Pipeline processor; Cache memory; Theoretical study; Chip; Addressing; Operation study; Energy dissipation; Complementary MOS technology; High speed; Coupling; Microprocessor; Timing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.375956

This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 /spl mu/m CMOS design rule.< >