A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS

A 1-GHz Razor FIR accelerator is implemented in a 65-nm CMOS process. Timing-error detection is implemented using Razor latches on critical paths. Real-time DSP systems necessitate fixed-latency error-correction, which is achieved using a combination of two distinct mechanisms. First, marginal timin...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 49; no. 1; pp. 84 - 94
Main Authors Whatmough, Paul N., Das, Shidhartha, Bull, David M.
Format Journal Article
LanguageEnglish
Published IEEE 01.01.2014
Subjects
Adaptive circuits
Clocks
Digital signal processing
digital signal processing (DSP)
dynamic voltage and frequency scaling (DVFS)
Error correction
finite-impulse response (FIR)
Image edge detection
Latches
low-power digital
Pipelines
process variation
process variations
razor
resilient circuits
resilient design
supply voltage droop
temperature variation
Timing
timing error correction
timing error detection
timing errors
variation tolerance
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Summary:A 1-GHz Razor FIR accelerator is implemented in a 65-nm CMOS process. Timing-error detection is implemented using Razor latches on critical paths. Real-time DSP systems necessitate fixed-latency error-correction, which is achieved using a combination of two distinct mechanisms. First, marginal timing violations are corrected using a time-borrow tracking algorithm that uses timing-error detection information to track excessive time borrowing. Second, persistent unresolved time borrowing is corrected at the end of the pipeline using a low-overhead approximate error-correction stage which is based on interpolation. Measurements at peak throughput of over 1 GS/s demonstrate an energy-efficiency improvement of 37%, while maintaining 10% supply voltage margin.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2013.2284364