Application-Specific Heterogeneous Network-on-Chip Design

As a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips. A challenge in application-specific NoC design is to find the right balance among different tradeoffs,...

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Bibliographic Details
Published inComputer journal Vol. 57; no. 8; pp. 1117 - 1131
Main Authors Demirbas, D., Akturk, I., Ozturk, O., Gudukbay, U.
Format Journal Article
LanguageEnglish
Published Oxford Oxford Publishing Limited (England) 01.08.2014
Subjects
Communication
Design specifications
Energy consumption
Integrated circuits
Multiprocessing
Scalability
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Summary:As a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips. A challenge in application-specific NoC design is to find the right balance among different tradeoffs, such as communication latency, power consumption and chip area. We propose a novel approach that generates latency-aware heterogeneous NoC topology. Experimental results show that our approach improves the total communication latency up to 27% with modest power consumption.
Bibliography:SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 14
ISSN:0010-4620
1460-2067
DOI:10.1093/comjnl/bxt011