Wafer-scale and environmentally-friendly deposition methodology for extremely uniform, high-performance transistor arrays with an ultra-low amount of polymer semiconductors

• Published in: Journal of materials chemistry. C, Materials for optical and electronic devices Vol. 3; no. 12; pp. 2817 - 2822
• Main Authors: Cho, Jangwhan, Ko, Yeongun, Cheon, Kwang Hee, Yun, Hui-Jun, Lee, Han-Koo, Kwon, Soon-Ki, Kim, Yun-Hi, Chang, Suk Tai, Chung, Dae Sung
• Format: Journal Article
• Language: English
• Published: 01.01.2015
• Subjects: Arrays; Deposition; Electronic devices; Failure; Semiconductor devices; Semiconductors; Strategy; Threshold voltage; Transistors
• ISSN: 2050-7526; 2050-7534
• DOI: 10.1039/C4TC02674H

We report on a new class of microliter-scale solution processes for fabricating highly uniform and large-area transistor arrays with extremely low consumption of semiconducting polymers. These processes are accomplished by applying a vertical phase separation of polymers with an environmentally benign solvent, a random copolymerization strategy between two highly conductive repeating units, and a meniscus-dragging deposition technique. The successful realization of these three processes, as confirmed by the structural and morphological in-depth characterizations, has enabled the fabrication of high-performance polymeric field-effect transistors that were uniformly distributed, without a single failure, on a 4 inch wafer using only 40 μg of semiconducting polymers. The resulting transistor arrays showed an average mobility of 0.28 cm 2 V −1 s −1 , with a low standard deviation of 0.04, as well as ultra-uniform near-zero threshold voltages. Our simple strategy shows great promise for fabricating large-scale organic electronic devices in the future using a truly low-cost process.