A floating track method for complete routing
A “floating track” method is proposed for VLSI routing, which ensures a 100 percent connection ratio. This method automatically provides a connection path on the cells by using a line‐search algorithm and solves the problem of unconnected pin pairs by adding extra wiring tracks. Prevention rules and...
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| Published in | Electronics & communications in Japan. Part 2, Electronics Vol. 69; no. 8; pp. 20 - 29 |
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| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
New York
Wiley Subscription Services, Inc., A Wiley Company
1986
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| Online Access | Get full text |
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| Summary: | A “floating track” method is proposed for VLSI routing, which ensures a 100 percent connection ratio. This method automatically provides a connection path on the cells by using a line‐search algorithm and solves the problem of unconnected pin pairs by adding extra wiring tracks. Prevention rules and correction procedures are provided for the wiring shorts and disconnections caused by the track addition. Based on the distribution of the track addition requirement calculated from the location and status of the search line, a fast algorithm is developed for determining the location of the additional tracks. With this algorithm a number of unconnected pin pairs can be connected quickly without a penalty in chip size. The layout result of a 20‐Kgate 4‐layered VLSI confirms the usefulness of this method for designing high‐density multilayered VLSIs. |
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| Bibliography: | istex:8CB7157BA7C3DBD6D1A512147222E8992F9A30AE ark:/67375/WNG-KN9NCG0Z-C ArticleID:ECJB4420690803 Tadashi Sone. Received B.S. and M.S. degrees in electrical engineering from Nihon University, Tokyo, Japan, in 1974 and 1976. Joined NTT Musashino Electrical Communications Laboratories, Tokyo, Japan, in 1976, and engaged in research on the logic and layout design of VLSIs. Currently, as research engineer, he is assistant to the Executive Manager of the Electronic Equipment Department, Electronics and Mechanics Technology Laboratories. Kiyoshi Nakabayashi. Received B.S. and M.S. degrees in applied physics from Tokyo Institute of Technology, Japan, in 1980 and 1982. Since joining NTT Musashino Electrical Communications Laboratories, Tokyo, Japan, in 1982, he has been engaged in research on LSI layout design. Currently, he is an engineer of the Pattern Processing Section, Knowledge Engineering Department, Communications and Information Processing Laboratories. |
| ISSN: | 8756-663X 1520-6432 |
| DOI: | 10.1002/ecjb.4420690803 |