A method of hazard detection by five-valued logic simulation based on the TRF delay model

This paper proposes an efficient method to detect the hazard existing in the logic circuit using the five‐valued logic simulator. The proposed method is effective in logic verification for the combinational and asynchronous and sequential logic circuits as well as the verification for the hazard (ra...

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Bibliographic Details
Published inElectronics & communications in Japan. Part 3, Fundamental electronic science Vol. 75; no. 3; pp. 1 - 12
Main Authors Kang, Min Sup, Deguchi, Hiroshi, Shirakawa, Isao
Format Journal Article
LanguageEnglish
Published New York Wiley Subscription Services, Inc., A Wiley Company 01.03.1992
Subjects
Five-valued logic simulator
hazard detection
logic circuits
race phenomenon
rise/fall (R/F) delay
spike filtering
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Summary:This paper proposes an efficient method to detect the hazard existing in the logic circuit using the five‐valued logic simulator. The proposed method is effective in logic verification for the combinational and asynchronous and sequential logic circuits as well as the verification for the hazard (race). Using the proposed method, the timing of the logic circuit is analyzed, including the rise/fall delay considering the signal transition time. The hazard is detected based on the output of the gate and the scheduled time. Also discussion is a method of event cancellation, which is a problem in the delayed simulation. Through the results of experiments using several circuits, the proposed algorithm is shown to be useful.
Bibliography:ArticleID:ECJC4430750301
istex:79F1F1BAC8EDB595612ED7676B32445E74342EE4
ark:/67375/WNG-SF2M8WDR-Q
Exercise in Graph Theory
co‐author of
Min Sup Kang graduated in 1979 from the Dept. Elect. Comm., Kanwoon Institute of Technology, and obtained a Master's degree in 1984 from Hanyan Indust. University. He is presently in the doctoral program at Osaka University. He was a Researcher from 1984 to 1988 at Korean Elect. Comm. Lab. and during this period, from 1986 to 1987, a Visiting Researcher at Osaka University. He is engaged in research on logic simulation and fault diagnosis of VLSI. He is a member of the Korean Soc. Electronic Eng. and of IEEE.
(Corona Publ. Co.), and other books.
Isao Shirakawa graduated in 1963 from the Dept. Electronic Eng., Fac. Eng., Osaka University, where he obtained a Master's degree in 1965 and a Dr. of Eng. degree in 1968. He was an Assistant in 1968, Assoc. prof. in 1973, and a Professor in 1987 at Osaka University. He is engaged in education and research on network theory, theory of graphs, and CAD of electrical systems. He was a Visiting Researcher from 1974 to 1975 at the University of California, Berkeley, U.S.A. He is the author of
Hiroshi Deguchi graduated in 1981 from the Dept. Electronic Eng., Fac. Eng., Osaka University, where he obtained a Dr. of Eng. degree in 1986. He was a Visiting Researcher in 1986 at the University of Illinois, U.S.A. He was an Assistant in 1987, Fac. Eng., Osaka University. He is engaged in research on parallel processing systems and computer‐aided design. He is a member of the Inf. Proc. Soc. Jap.; IEEE; and ACM.
Basis of Circuit Theory
ISSN:1042-0967
1520-6440
DOI:10.1002/ecjc.4430750301