Compact On-Wafer Test Structures for Device RF Characterization

• Published in: IEEE transactions on electron devices Vol. 64; no. 8; pp. 3101 - 3107
• Main Authors: Kazemi Esfeh, Babak, Ben Ali, Khaled, Raskin, Jean-Pierre
• Format: Journal Article
• Language: English
• Published: IEEE 01.08.2017
• Subjects: 50-μm-pitch RF probes; coplanar wave-guide (CPW) transmission lines; Coplanar waveguides; MOSFET; on-wafer RF characterization; Probes; Radio frequency; RF MOSFET parasitic extraction; RF pads; RF test structures; Scattering parameters; silicon-on-insulator (SOI) technology; Substrates; Transmission line measurements; trap-rich high-resistivity SOI substrate
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2017.2717196

The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50-μm-pitch RF probes. It is shown that by using these new test structures, the layout geometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100-150 μm-pitch RF probes. 50-μm-pitch de-embedding structures have been implemented on 0.18-μm RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of traprich SOI substrates is analyzed under small-and large-signal conditions.