Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty

Strategies to mitigate soft errors in combinational logic have resulted in large performance penalties and increases in design time. This study alleviates these issues by using standard cells to selectively harden vulnerable nodes in combinational logic. Results indicate that replacing two-input gat...

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Bibliographic Details
Published inIEEE transactions on nuclear science Vol. 60; no. 4; pp. 2776 - 2781
Main Authors Limbrick, Daniel B., Mahatme, N. N., Robinson, W. H., Bhuva, B. L.
Format Journal Article
LanguageEnglish
Published IEEE 01.08.2013
Subjects
Capacitance
Combinational logic
Delay
Integrated circuit reliability
MOSFETs
pulse width
reliability-aware synthesis
single event transient
soft error
Transient analysis
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Summary:Strategies to mitigate soft errors in combinational logic have resulted in large performance penalties and increases in design time. This study alleviates these issues by using standard cells to selectively harden vulnerable nodes in combinational logic. Results indicate that replacing two-input gates with four-input equivalents reduces pulse widths by 5%-20% with less than 1% power overhead. Additionally, this paper demonstrates reliability gains that can be made at the synthesis level under tight performance constraints.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2013.2240699