Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction
In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be...
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| Published in | Journal of semiconductor technology and science Vol. 23; no. 4; pp. 207 - 214 |
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| Main Authors | , , , , , , |
| Format | Journal Article |
| Language | English |
| Published |
대한전자공학회
01.08.2023
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| Subjects | |
| Online Access | Get full text |
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| Abstract | In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm. KCI Citation Count: 0 |
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| AbstractList | In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm. KCI Citation Count: 0 |
| Author | Hyunwoo Kim Jang Hyun Kim Seongjae Cho Garam Kim Chaewon Yun Il Hwan Cho Sangwan Kim |
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| Keywords | junction underlap TCAD device simulation line tunneling fieldeffect transistor (LTFET) Dual workfunction low-power operation |
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| Title | Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction |
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