Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction

In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be...

Full description

Saved in:
Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 23; no. 4; pp. 207 - 214
Main Authors Yun, Chaewon, Kim, Sangwan, Cho, Seongjae, Cho, Il-Hwan, Kim, Hyunwoo, Kim, Jang-Hyun, Kim, Garam
Format Journal Article
LanguageEnglish
Published 대한전자공학회 01.08.2023
Subjects
전기공학
junction underlap
TCAD device simulation
line tunneling fieldeffect transistor (LTFET)
Dual workfunction
low-power operation
Online AccessGet full text

Cover

More Information
Summary:In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm. KCI Citation Count: 0
ISSN:1598-1657
2233-4866
2233-4866
1598-1657
DOI:10.5573/JSTS.2023.23.4.207