Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures

• Published in: IEEE computer architecture letters Vol. 14; no. 2; pp. 136 - 139
• Main Authors: Diamantopoulos, Dionysios, Xydis, Sotirios, Siozios, Kostas, Soudris, Dimitrios
• Format: Journal Article
• Language: English
• Published: IEEE 01.07.2015
• Subjects: dynamic memory management; Dynamic scheduling; Field programmable gate arrays; high-level synthesis; many-accelerator architectures; Memory management; Network architecture; Resource management; System-on-chip; Throughput; Many-accelerator architectures; high-level synthesis; dynamic memory management
• ISSN: 1556-6056; 1556-6064
• DOI: 10.1109/LCA.2015.2410791

Many-Accelerator (MA) systems have been introduced as a promising architectural paradigm that can boost performance and improve power of general-purpose computing platforms. In this paper, we focus on the problem of resource under-utilization, i.e. Dark Silicon, in FPGA-based MA platforms. We show that except the typically expected peak power budget, on-chip memory resources form a severe under-utilization factor in MA platforms, leading up to 75 percent of dark silicon. Recognizing that static memory allocation-the de-facto mechanism supported by modern design techniques and synthesis tools-forms the main source of memory-induced Dark Silicon, we introduce a novel framework that extends conventional high level synthesis (HLS) with dynamic memory management (DMM) features, enabling accelerators to dynamically adapt their allocated memory to the runtime memory requirements, thus maximizing the overall accelerator count through effective sharing of FPGA's memories resources. We show that our technique delivers significant gains in FPGA's accelerators density, i.e. 3.8×, and application throughput up to 3.1× and 21.4× for shared and private memory accelerators.