Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI

• Published in: IEEE electron device letters Vol. 38; no. 11; pp. 1555 - 1558
• Main Authors: Zhang, Wentong, Zhan, Zhenya, Yu, Yang, Cheng, Shikang, Gu, Yan, Zhang, Sen, Luo, Xiaorong, Li, Zehong, Qiao, Ming, Li, Zhaoji, Zhang, Bo
• Format: Journal Article
• Language: English
• Published: IEEE 01.11.2017
• Subjects: Breakdown voltage; breakdown voltage (VB); Dielectrics; Doping; Electric fields; Optimization; Silicon-on-insulator; sp; specific on-resistance (Ron; Substrates; Superjunction; T-SJ LDMOS; thin layer SOI
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2017.2751571

A novel superjunction (SJ) lateral double-diffused MOSFET ( >950 V) with a thin layer SOI combining the advantage of low specific on-resistance R on,sp of the SJ and the high breakdown voltage VB of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate model, the optimized SJ endows the device with a respectably reduced R on,sp without sacrificing V B . Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field principle to carry out a high V B . The experimental results exhibit a R on,sp of 145 mg·cm 2 with a V B of 977 V. This represents a reduction in R on,sp by 18.1% when compared with the theoretical R on,sp ∝ V B 2.5 "silicon limit".