A Low-power Incremental Delta-sigma ADC with Adaptive Biasing for CMOS Image Sensors

This paper presents the design and fabrication of a low-power incremental delta-sigma analog-to-digital converter (ADC) with an adaptive bias technique suitable for complimentary metal-oxide semiconductor (CMOS) image sensors (CISs). The adaptive biasing circuitry provides the amplifier with a predi...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 23; no. 5; pp. 314 - 321
Main Authors Seo, Dong-Hwan, Kim, Jung-Gyun, Lee, Byung-Geun
Format Journal Article
LanguageEnglish
Published 대한전자공학회 01.10.2023
Subjects
전기공학
analog-to-digital converter
CMOS image sensor
incremental deltasigma
Adaptive biasing
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Summary:This paper presents the design and fabrication of a low-power incremental delta-sigma analog-to-digital converter (ADC) with an adaptive bias technique suitable for complimentary metal-oxide semiconductor (CMOS) image sensors (CISs). The adaptive biasing circuitry provides the amplifier with a predicted minimum current value required for the integrator output to settle; this optimized current flows through the amplifier and reduces power consumption by 40%. A prototype ADC fabricated using a 0.18 µm CMOS process, achieves an SNDR of 65 dB at a sampling frequency of 25 MHz and consumes 13.5 µW from a 1.8 V power supply. The measured differential and integral nonlinearities are +0.31/-0.42 and +0.62/-0.75 at a 12-bit accuracy, respectively. KCI Citation Count: 0
ISSN:1598-1657
2233-4866
2233-4866
1598-1657
DOI:10.5573/JSTS.2023.23.5.314