On the Impact of Through-Silicon-Via-Induced Stress on 65-nm CMOS Devices

• Published in: IEEE electron device letters Vol. 34; no. 1; pp. 18 - 20
• Main Authors: Weerasekera, R., Hong Yu Li, Lim Wei Yi, Hu Sanming, Jinglin Shi, Je Minkyu, Keng Hwa Teo
• Format: Journal Article
• Language: English
• Published: IEEE 01.01.2013
• Subjects: Foundries; Keep-out zone (KOZ); Logic gates; MOSFETs; Silicon; Stress; three-dimensional integrated circuits (ICs); through-silicon via (TSV); Through-silicon vias
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2012.2228158

Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm, respectively. Measured change of saturation current (I on ) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between -55°C and 125 °C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.