A 25-Gb/s PAM-4 Baud-rate CDR with High Jitter Tolerance using Shared Sampler Method

This paper proposes a pulse amplitude modulation-4 (PAM-4) baud-rate clock and data recovery (CDR) circuit with improved jitter tolerance using a shared sampler method. In the proposed design technique, each sampler output is used simultaneously for data decoding and phase detection. Since all sampl...

Full description

Saved in:
Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 24; no. 3; pp. 208 - 217
Main Authors Cho, Seoung-Geun, Kang, Jin-Ku
Format Journal Article
LanguageEnglish
Published 대한전자공학회 01.06.2024
Subjects
전기공학
CMOS
time-domain
transition density
PAM-4 receiver
high-speed
baud-rate CDR
jitter tolerance
Online AccessGet full text

Cover

More Information
Summary:This paper proposes a pulse amplitude modulation-4 (PAM-4) baud-rate clock and data recovery (CDR) circuit with improved jitter tolerance using a shared sampler method. In the proposed design technique, each sampler output is used simultaneously for data decoding and phase detection. Since all samplers are used for phase detection, it has improved jitter tolerance based on high transition density. In this design, the transition density is 0.375. In addition, only four samplers are used per UI, which enables an energy efficient CDR design. Furthermore, the proposed phase detector (PD) minimizes CDR lock point fluctuations by employing pattern-based PD. The receiver with proposed CDR is implemented in a 65-nm CMOS process and has a target of 25 Gb/s data rate. The power consumption of the receiver is 19.6 mW with -7.1 dB channel loss. The energy efficiency of the receiver is 0.784 pJ/bit. KCI Citation Count: 0
ISSN:1598-1657
2233-4866
2233-4866
1598-1657
DOI:10.5573/JSTS.2024.24.3.208