High-performance Parallel Concatenated Polar-CRC Decoder Architecture

In this paper, a novel parallel encoding and decoding method is proposed, which uses concatenated polar-cyclic redundancy check (polar-CRC) codes for high throughput polar decoder implementation. When compared to previous works, the proposed method considerably reduces latency and improves throughpu...

Full description

Saved in:
Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 18; no. 5; pp. 560 - 567
Main Authors Oh, Seunghun, Lee, Hanho
Format Journal Article
LanguageEnglish
Published 대한전자공학회 01.10.2018
Subjects
전기공학
concatenated
successive cancellation decoding
Polar codes
CRC codes
Online AccessGet full text

Cover

More Information
Summary:In this paper, a novel parallel encoding and decoding method is proposed, which uses concatenated polar-cyclic redundancy check (polar-CRC) codes for high throughput polar decoder implementation. When compared to previous works, the proposed method considerably reduces latency and improves throughput. A parallel concatenated polar-CRC decoder architecture based on the proposed method is presented and synthesized using 65-nm CMOS process technology. Synthesis results show that the proposed architecture has 4.9 times the data throughput and 4.5 times the hardware efficiency of conventional SC polar decoder architecture. KCI Citation Count: 0
ISSN:1598-1657
2233-4866
DOI:10.5573/JSTS.2018.18.5.560