Performance Optimization of IPN in RF PLL using Bayesian Optimization

• Published in: Journal of semiconductor technology and science Vol. 24; no. 2; pp. 69 - 75
• Main Authors: Yoon, Ji-Sub, Choi, Doing-In, Park, Seungyoung, Hwang, In-Chul
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.04.2024
• Subjects: 전기공학; phase-locked loop; integrated phase noise (IPN); delta-sigma modulator; Bayesian optimization; phase noise
• ISSN: 1598-1657; 2233-4866; 2233-4866; 1598-1657
• DOI: 10.5573/JSTS.2024.24.2.69

The performance optimization of a circuit in a short time is one of the important issues for IC testing. Traditional methods depend on domain knowledge and exhaustive search (ES) for feasible parameters. In this paper, we proposed the sub-optimal control of the integrated phase noise (IPN) characteristics of RF phase lock loop (PLL) using a Bayesian optimization. For data acquisition, we designed an autonomous measurement platform based on general purpose interface bus (GPIB) and Python. Using our algorithm, we achieved performance within around 3 dB of the optimal at the 95th percentile and reduced the search time for optimal parameters by at least 98.75% compared to the ES method. KCI Citation Count: 0