An IP-oriented 11-bit 160 MS/s 2-channel current-steering DAC

This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of cu...

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Bibliographic Details
Published inJournal of semiconductors Vol. 35; no. 12; pp. 123 - 127
Main Author 许宁 李福乐 张春 王志华
Format Journal Article
LanguageEnglish
Published 01.12.2014
Subjects
Channels
Circuit design
CMOS工艺
Current sources
DAC
Linearity
Matching
Mathematical analysis
Nonlinearity
Semiconductors
双通道
布局布线
模拟转换器
电流输出
积分非线性
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Summary:This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL ≤60.25 LSB, INL ≤6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm^2 in a 1P-8M 55 nm CMOS process.
Bibliography:Xu Ning,Li Fule,Zhang Chun,Wang Zhihua（Institute of Microelectronics, Tsinghua University, Beijing 100084, China）
This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL ≤60.25 LSB, INL ≤6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm^2 in a 1P-8M 55 nm CMOS process.
11-5781/TN
current-steering DAC; IP; matching; area optimization; mapping
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:1674-4926
DOI:10.1088/1674-4926/35/12/125011