Latch-Up in CMOS Integrated Circuits

The parasitic transistors and pnpn paths present on junction-isolated CMOS circuits have been identified and studied quantitatively. Active SCR structures exist which can be triggered electrically or by a radiation pulse. Detailed studies of SCR paths have been performed on two circuits, the CD4007A...

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Bibliographic Details
Published inIEEE transactions on nuclear science Vol. 20; no. 6; pp. 293 - 299
Main Authors Gregory, B. L., Shafer, B. D.
Format Journal Article
LanguageEnglish
Published IEEE 01.01.1973
Subjects
Bipolar integrated circuits
CMOS integrated circuits
CMOS technology
Dielectrics
Diodes
Electric resistance
Integrated circuit technology
Isolation technology
Pulsed power supplies
Thyristors
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Summary:The parasitic transistors and pnpn paths present on junction-isolated CMOS circuits have been identified and studied quantitatively. Active SCR structures exist which can be triggered electrically or by a radiation pulse. Detailed studies of SCR paths have been performed on two circuits, the CD4007A and the CD4041A, to relate geometrical and materials parameters to latch-up sensitivity. Both normal bias conditions and bias optimum for obtaining SCR action are employed. Several techniques are proposed to eliminate radiation-induced latchup in future CMOS designs.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.1973.4327410