A 4 GHz 32 bit direct digital frequency synthesizer based on a novel architecture

This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collectio...

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Bibliographic Details
Published inJournal of semiconductors Vol. 34; no. 11; pp. 136 - 141
Main Author 武锦 陈建武 吴旦昱 周磊 江帆 金智 刘新宇
Format Journal Article
LanguageEnglish
Published 01.11.2013
Subjects
32位
Architecture (computers)
Chips
Digital
GHz
Mathematical analysis
Nonlinearity
ROM
Segments
Semiconductors
SFDR
Stores
初始值
架构
直接数字频率合成器
芯片面积
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Summary:This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 #m GaAs HBT technology. The measurement shows an average spurious-free dynamic range （SFDR） of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a --4.9 V power supply.
Bibliography:direct digital frequency synthesis; read-only memory; digital-to-analog converter; gallium arsenide; heterojunction bipolar transistor
This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 #m GaAs HBT technology. The measurement shows an average spurious-free dynamic range （SFDR） of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a --4.9 V power supply.
Wu Jin, Chen Jianwu, WH Danyu, Zhou Lei, Jiang Fan, Jin Zhi, Liu Xinyu（ 1 Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China 2 Key Laboratory of Microelectronics Devices ＆ Integrated Technology, Beijing 100029, China）
11-5781/TN
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:1674-4926
DOI:10.1088/1674-4926/34/11/115007