A 0.6-V 8.3-ENOB asynchronous SAR ADC for biomedical applications

A microwatt asynchronous successive approximation register （SAR） analog-to-digital converter （ADC） is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power require- ments of biomedical systems. The tail capacitor of the DAC array is reused for least...

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Bibliographic Details
Published inJournal of semiconductors Vol. 35; no. 8; pp. 158 - 164
Main Author 宋焱 薛仲明 严鹏程 张珏颖 耿莉
Format Journal Article
LanguageEnglish
Published 01.08.2014
Subjects
ADC
Arrays
Capacitance
Clock generators
CMOS技术
Electric potential
Logic
Power consumption
Sampling
SAR
Semiconductors
低功耗
异步
数字转换器
时钟发生器
生物医学应用
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ISSN1674-4926
DOI10.1088/1674-4926/35/8/085007

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Summary:A microwatt asynchronous successive approximation register （SAR） analog-to-digital converter （ADC） is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power require- ments of biomedical systems. The tail capacitor of the DAC array is reused for least significant bit conversion to decrease the total DAC capacitance thus reducing the power. Asynchronous control logic avoids the high frequency clock generator and further reduces the power consumption. The prototype ADC is fabricated with a standard 0.18 μm CMOS technology. Experimental results show that it achieves an ENOB of 8.3 bit at a 300-kS/s sampling rate. Very low power consumption of 3.04 μW is achieved, resulting in a figure of merit of 32 fJ/conv.-step.
Bibliography:A microwatt asynchronous successive approximation register （SAR） analog-to-digital converter （ADC） is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power require- ments of biomedical systems. The tail capacitor of the DAC array is reused for least significant bit conversion to decrease the total DAC capacitance thus reducing the power. Asynchronous control logic avoids the high frequency clock generator and further reduces the power consumption. The prototype ADC is fabricated with a standard 0.18 μm CMOS technology. Experimental results show that it achieves an ENOB of 8.3 bit at a 300-kS/s sampling rate. Very low power consumption of 3.04 μW is achieved, resulting in a figure of merit of 32 fJ/conv.-step.
Song Yan, Xue Zhongming, Yan Pengcheng Zhang Jueylng, and Geng Li（Department of M icroelectronics, Xi＇an Jiaotong University, Xi＇an 710049, China）
11-5781/TN
SAR ADC, low voltage; low power; biomedical system
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ISSN:1674-4926
DOI:10.1088/1674-4926/35/8/085007