An FPGA-Based Hardware Architecture of Gaussian-Adaptive Bilateral Filter for Real-Time Image Denoising

• Published in: IEEE access Vol. 12; pp. 115277 - 115285
• Main Authors: Xie, Ailin, Zhang, Ao, Mei, Guohui
• Format: Journal Article
• Language: English
• Published: IEEE 2024
• Subjects: Bilateral filter; Computer architecture; edge-preserving; Field programmable gate arrays; field-programmable gate array (FPGA); Filtering algorithms; Hardware; image denoising; Information filters; Kernel; Low-pass filters
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2024.3443999

The bilateral filter exhibits remarkable efficacy in noise suppression and edge preservation. This article proposes a hardware architecture based on field-programmable gate array (FPGA) for a modified bilateral filter. To enhance the efficacy of the bilateral filter, the Gaussian-adaptive Bilateral Filter (GABF) is employed as a modified filtering method. Approximating the filter weights using look-up tables (LUTs) results in reduced storage requirements and eliminates the need for complex exponential weight calculations. Moreover, the GABF is markedly accelerated by the highly parallel functional modules and LUTs. In addition to the aforementioned features, the GABF is implemented as a parallel architecture, which results in a reduction in hardware resource utilization compared to previous works. The results of the image quality analysis demonstrate that this article can achieve superior image quality compared with state-of-the-art works. The implementation results indicate that the proposed architecture is capable of performing real-time denoising at a frame rate of 95.65 fps for a <inline-formula> <tex-math notation="LaTeX">640\times 480 </tex-math></inline-formula> video with a power dissipation of 93.22 mW.