A low power 11-bit 100 MS/s SAR ADC IP

This paper presents a dual-channel 11-bit 100 MS/s hybrid SAR ADC IR Each channel adopts flash- SAR architecture for high speed, low power and high linearity. Dynamic comparators in the coarse flash ADC and the fine SAR ADC further contribute to the reduction of power consumption. A gate-controlled...

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Bibliographic Details
Published inJournal of semiconductors Vol. 36; no. 2; pp. 130 - 134
Main Author 王亚 薛春莹 李福乐 张春 王志华
Format Journal Article
LanguageEnglish
Published 01.02.2015
Subjects
ADC
Channels
CMOS技术
Comparators
Consumption
High speed
Linearity
Logic
Oscillators
SAR
Semiconductors
低功耗
动态比较器
双通道
环形振荡器
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Summary:This paper presents a dual-channel 11-bit 100 MS/s hybrid SAR ADC IR Each channel adopts flash- SAR architecture for high speed, low power and high linearity. Dynamic comparators in the coarse flash ADC and the fine SAR ADC further contribute to the reduction of power consumption. A gate-controlled ring oscillator generates a multi-phase clock for SAR logic, thereby allowing it to asynchronously trigger the comparator in the fine SAR ADC in high speed. MOM capacitors with a fully shielded structure provide enough matching accuracy without the need for calibration. This design was fabricated in SMIC 55 nm low leakage CMOS technology and the active area of dual-channel （I-Q） ADC is 0.35 mm2, while the core area is 0.046 mm2. It consumes 2.92 mA at a 1.2 V supply, for dual-channel too. The effective number of bits （ENOB） is 9.90 bits at 2.4 MHz input frequency, and 9.34 bits at 50 MHz, leading to a FOM of 18.3 fJ/conversion-step.
Bibliography:Wang Ya, Xue Chunying, Li Fule, Zhang Chun,Wang Zhihua
This paper presents a dual-channel 11-bit 100 MS/s hybrid SAR ADC IR Each channel adopts flash- SAR architecture for high speed, low power and high linearity. Dynamic comparators in the coarse flash ADC and the fine SAR ADC further contribute to the reduction of power consumption. A gate-controlled ring oscillator generates a multi-phase clock for SAR logic, thereby allowing it to asynchronously trigger the comparator in the fine SAR ADC in high speed. MOM capacitors with a fully shielded structure provide enough matching accuracy without the need for calibration. This design was fabricated in SMIC 55 nm low leakage CMOS technology and the active area of dual-channel （I-Q） ADC is 0.35 mm2, while the core area is 0.046 mm2. It consumes 2.92 mA at a 1.2 V supply, for dual-channel too. The effective number of bits （ENOB） is 9.90 bits at 2.4 MHz input frequency, and 9.34 bits at 50 MHz, leading to a FOM of 18.3 fJ/conversion-step.
11-5781/TN
analog-to-digital converter; SAR; hybrid ADC
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:1674-4926
DOI:10.1088/1674-4926/36/2/025003