A 0.18μm CMOS transmit physical coding sublayer IC for 100G Ethernet

• Published in: Journal of semiconductors Vol. 37; no. 3; pp. 103 - 109
• Main Author: 阮伟华 胡庆生
• Format: Journal Article
• Language: English
• Published: 01.03.2016
• Subjects: Circuits; CMOS; CMOS工艺; Coding; Ethernet; Gearboxes; IEEE; Logic; Optimization; Semiconductors; 以太网; 传输; 流水线结构; 物理编码子层; 设计方法
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/37/3/035005

This paper presents a transmit physical coding sublayer（PCS） circuit for 100 G Ethernet. Based on the4×25 Gb/s architecture according to the IEEE P802.3ba and IEEE P802.3bm-（TM）/D1.1 standards, this PCS circuit is designed using a semi-custom design method and consists of 4 modules including 64B/66 B encoder, scrambler,multiple lanes distribution and 66 ： 8 gearbox. By using the pipeline structure and several optimization techniques,the working speed of the circuit is increased significantly. The parallel scrambling combined with logic optimization also improve the performance. In addition, a kind of phase-independent structure is employed in the design of the gearbox to ensure it can work stably and reliably at high frequency. This PCS circuit has been fabricated based on0.18μm CMOS technology and the total area is 1.7×1.7 mm^2. Measured results show that the circuit can work properly at 100 Gb/s and the power consumption is about 284 m W with a 1.8 V supply.