Impact of near interface defects on NO annealed SiC MOSFET mobility

• Published in: Microelectronics and reliability Vol. 173; p. 115841
• Main Authors: Wen, Yu-Xin, Tsui, Bing-Yue, Cheung, Kin P.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.10.2025
• Subjects: Channel mobility; Charge trapping; Fast Id-Vg measurement; Near-interface traps (NITs); NO annealing; Oxide reliability; SiC MOSFET; Channel mobility; NO annealing; Near-interface traps (NITs); SiC MOSFET; Oxide reliability; Fast Id-Vg measurement; Charge trapping
• ISSN: 0026-2714
• DOI: 10.1016/j.microrel.2025.115841

The cause of low mobility in SiC MOSFETs, particularly after post-oxidation nitric oxide (NO) annealing, remains a critical question in wide-bandgap device reliability. Previous reports have attributed poor mobility to the formation of fast near-interface traps (NITs) introduced by NO annealing. In this study, we utilize fast drain current–gate voltage (Id-Vg) measurements, which has a simple interpretation, to directly probe these NITs to check if these assertions are true. Our fast drain current–gate voltage measurements show that on the time scales of 10 ns to 500 ns, filling near interface traps leads to <10 % reduction in the mobility, implying that such traps cannot explain the poor mobility in SiC MOSFETs. This finding challenges the attribution of poor mobility solely to fast NITs and point toward alternative mechanisms, such as above band edge states. •Fast Id–Vg pulses used to probe near-interface traps in NO-annealed SiC MOSFETs.•Drain current decay under 10 ns–500 ns shows <10 % mobility degradation.•Results indicate fast NITs are not primary cause of poor mobility.•Study questions prior assumptions about NO-induced trap-related degradation.