A digital background calibration algorithm of a pipeline ADC based on output code calculation

This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter（ADC）.The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic.Based on the analy...

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Bibliographic Details
Published inJournal of semiconductors Vol. 33; no. 11; pp. 110 - 114
Main Author 邵健健 李玮韬 孙操 李福乐 张春 王志华
Format Journal Article
LanguageEnglish
Published 01.11.2012
Subjects
ADC
Algorithms
Calibration
Digital
Errors
Linearity
Logic
Noise levels
Semiconductors
代码
基础
校准
流水线
算法
计算
输出
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Summary:This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter（ADC）.The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic.Based on the analysis of the output codes,the calibration logic estimates the bit weight of each stage and corrects the outputs.An experimental 14-bit pipelined ADC is fabricated to verify the algorithm.The results show that INL errors drop from 20 LSB to 1.7 LSB,DNL errors drop from 2 LSB to 0.4 LSB,SNDR grows from 57 to 65.7 dB and THD drops from -58 to -81 dB.The linearity of the pipelined ADC is improved significantly.
Bibliography:11-5781/TN
pipeline ADC output code calculation background calibration
This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter（ADC）.The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic.Based on the analysis of the output codes,the calibration logic estimates the bit weight of each stage and corrects the outputs.An experimental 14-bit pipelined ADC is fabricated to verify the algorithm.The results show that INL errors drop from 20 LSB to 1.7 LSB,DNL errors drop from 2 LSB to 0.4 LSB,SNDR grows from 57 to 65.7 dB and THD drops from -58 to -81 dB.The linearity of the pipelined ADC is improved significantly.
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ISSN:1674-4926
DOI:10.1088/1674-4926/33/11/115010