Optimised design of ECL gates with power constraint

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Bibliographic Details
Published inElectronics letters Vol. 40; no. 19; pp. 1169 - 1170
Main Authors GRASSO, A. D, PALUMBO, G
Format Journal Article
LanguageEnglish
Published London Institution of Electrical Engineers 16.09.2004
Subjects
Applied sciences
Circuit properties
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Switching, multiplexing, switched capacity circuits
Logic circuit
Emitter coupled logic
n p n transistor
Multiplexer
Logic gate
SPICE
Bipolar technology
Delay time
Low-power electronics
Optimization
Optimal design
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ISSN:0013-5194
1350-911X
DOI:10.1049/el:20045930