A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS

• Published in: ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) pp. 323 - 326
• Main Authors: Oh, Dong-Ryeol, Kim, Jong-In, Seo, Min-Jae, Kim, Jin-Gwang, Ryu, Seung-Tak
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.09.2015
• Subjects: ADC; Analog to digital converter; Arrays; Calibration; Clocks; CMOS; Conferences; Delays; flash ADC; High speed; Interpolation; Noise levels; offset calibration; Offsets; Power consumption; Power demand; Time-domain analysis; time-interleaved ADC
• ISBN: 1467374709; 9781467374705
• ISSN: 1930-8833; 2643-1319
• DOI: 10.1109/ESSCIRC.2015.7313892

A 6-b 4x time-interleaved (TI) time-domain interpolating flash ADC is presented for high-speed applications. The dynamic-amplifier-structured voltage-to-time converter (VTC) enables linear zero-crossing interpolation in the time-domain with an interpolation factor of eight, resulting in reduced power consumption and area. A sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated zero-crossing accuracy. The prototype 6-bit 10-Gs/s 4x TI flash ADC was implemented in a 65-nm CMOS process and occupied 0.22 mm 2 including a 4-to-1 output MUX and 243-times output decimator. The ADC achieves SNDR of 28.9 dB at Nyquist input and a total power consumption of 63 mW under supplies of 0.85 V and 1.1 V for the ADC cores and clock generator + T/Hs, respectively.