An Automatic Test-Generation System for Large Digital Circuits

A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm. Fault simulation adopts a concurrent simulation adopts a concurrent simulation technique. The system consists of four major modules: fault modeling, random pattern generati...

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Published inIEEE design & test of computers Vol. 2; no. 5; pp. 54 - 60
Main Authors Funatsu, Shigehiro, Kawai, Masato
Format Journal Article
LanguageEnglish
Published IEEE Computer Society 01.01.1985
Subjects
Automatic testing
Circuit faults
Circuit simulation
Circuit testing
Digital circuits
Power generation
Power system modeling
Sequential analysis
System testing
Test pattern generators
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Abstract A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm. Fault simulation adopts a concurrent simulation adopts a concurrent simulation technique. The system consists of four major modules: fault modeling, random pattern generation, algorithmic pattern generation, and fault simulation. The system can be a powerful CAD tool and effectively generate test patterns for large sequential circuits with Scan Path.
AbstractList A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm. Fault simulation adopts a concurrent simulation adopts a concurrent simulation technique. The system consists of four major modules: fault modeling, random pattern generation, algorithmic pattern generation, and fault simulation. The system can be a powerful CAD tool and effectively generate test patterns for large sequential circuits with Scan Path.
Author Kawai, Masato
Funatsu, Shigehiro
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Cites_doi 10.1147/rd.104.0278
10.1109/PROC.1983.12531
10.1109/TC.1983.1676174
10.1109/MC.1974.6323496
10.1109/TC.1976.1674663
10.1109/TC.1981.1675757
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References ref8
ref7
ref9
eichelberger (ref3) 1977
ref6
stewart (ref4) 1978
ref5
ref1
murakami (ref10) 1980
funatsu (ref2) 1975
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  doi: 10.1109/MC.1974.6323496
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  year: 1975
  ident: ref2
  article-title: test-generation systems in japan
  publication-title: Proc 12th Design Automation Conf
  contributor:
    fullname: funatsu
– ident: ref9
  doi: 10.1109/TC.1976.1674663
– start-page: 152
  year: 1978
  ident: ref4
  article-title: application of scan set for error detection and diagnostics
  publication-title: Proc 1978 Semiconductor Test Conf
  contributor:
    fullname: stewart
– ident: ref5
  doi: 10.1109/TC.1981.1675757
– start-page: 462
  year: 1977
  ident: ref3
  article-title: a logic design structure for lsi testability
  publication-title: Proc 14th Design Automation Conf
  contributor:
    fullname: eichelberger
– start-page: 39
  year: 1980
  ident: ref10
  article-title: test generation procedure for lsi functional testing
  publication-title: IECEJ SSD80-13
  contributor:
    fullname: murakami
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Snippet A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm. Fault simulation adopts a...
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SubjectTerms Automatic testing
Circuit faults
Circuit simulation
Circuit testing
Digital circuits
Power generation
Power system modeling
Sequential analysis
System testing
Test pattern generators
Title An Automatic Test-Generation System for Large Digital Circuits
URI https://ieeexplore.ieee.org/document/4069661
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