An Automatic Test-Generation System for Large Digital Circuits

A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm. Fault simulation adopts a concurrent simulation adopts a concurrent simulation technique. The system consists of four major modules: fault modeling, random pattern generati...

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Bibliographic Details
Published inIEEE design & test of computers Vol. 2; no. 5; pp. 54 - 60
Main Authors Funatsu, Shigehiro, Kawai, Masato
Format Journal Article
LanguageEnglish
Published IEEE Computer Society 01.01.1985
Subjects
Automatic testing
Circuit faults
Circuit simulation
Circuit testing
Digital circuits
Power generation
Power system modeling
Sequential analysis
System testing
Test pattern generators
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Summary:A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm. Fault simulation adopts a concurrent simulation adopts a concurrent simulation technique. The system consists of four major modules: fault modeling, random pattern generation, algorithmic pattern generation, and fault simulation. The system can be a powerful CAD tool and effectively generate test patterns for large sequential circuits with Scan Path.
ISSN:0740-7475
1558-1918
DOI:10.1109/MDT.1985.294817