A low-resistance self-aligned T-shaped gate for high-performance sub-0.1-μm CMOS

• Published in: IEEE transactions on electron devices Vol. 44; no. 6; pp. 951 - 956
• Main Authors: Hisamoto, D., Umeda, K., Nakamura, Y., Kimura, S.
• Format: Journal Article
• Language: English
• Published: 01.06.1997
• ISSN: 0018-9383
• DOI: 10.1109/16.585550

This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1- mu m region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 mu m to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 mu m. Furthermore, we experimentally show that the high circuit speed of a sub-0.1- mu m gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability.