Simplified quantitative stress-induced leakage current (SILC) model for MOS devices

A simplified quantitative model for the steady-state component of stress-induced leakage current (SILC) in MOS capacitors with ultrathin oxide layers has been developed by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. By using our model, we reduced...

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Bibliographic Details
Published inMicroelectronics and reliability Vol. 46; no. 2; pp. 287 - 292
Main Authors Ossaimee, M., Kirah, K., Fikry, W., Girgis, A., Omar, O.A.
Format Journal Article
LanguageEnglish
Published Oxford Elsevier Ltd 01.02.2006
Elsevier
Subjects
Applied sciences
Compound structure devices
Dielectric, amorphous and glass solid devices
Electronics
Exact sciences and technology
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Ultrathin films
Gate current
Charge carrier trapping
Inelasticity
Oxide layer
Electric stress
Tunnel effect
MOS structure
Stress effects
Leakage current
Steady state
MOS capacitor
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Summary:A simplified quantitative model for the steady-state component of stress-induced leakage current (SILC) in MOS capacitors with ultrathin oxide layers has been developed by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. By using our model, we reduced the time of numerical calculations of SILC to 17% of the standard method while maintaining a high accuracy of the results. We also confirmed that the SILC component must not be neglected when calculating the gate current in modern devices, especially at low fields. Our simplified model helped us to investigate the dependence of SILC on the oxide field and the oxide thickness. We also shed some light on the reasons that cause the peak in the SILC–oxide thickness relation.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2005.07.007