A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs

• Published in: 2018 28th International Conference on Field Programmable Logic and Applications (FPL) pp. 451 - 4511
• Main Authors: Salami, Behzad, Unsal, Osman, Cristal, Adrian
• Format: Conference Proceeding Publication
• Language: English
• Published: IEEE 01.08.2018
• Subjects: Circuit faults; Field programmable gate arrays; FPGA; High performance computing; Informàtica; Power Consumption; Random access memory; Reliability; Supercomputadors; Supply Voltage; System-on-chip; Voltage control; Voltage measurement; Àrees temàtiques de la UPC
• ISBN: 9781538685174; 1538685175
• ISSN: 1946-1488
• DOI: 10.1109/FPL.2018.00085

The power consumption of digital circuits, e.g., Field Programmable Gate Arrays (FPGAs), is directly related to their operating supply voltages. On the other hand, usually, chip vendors introduce a conservative voltage guardband below the standard nominal level to ensure the correct functionality of the design in worst-case process and environmental scenarios. For instance, this voltage guardband is empirically measured to be 12%, 20%, and 16% of the nominal level in commercial CPUs [1], Graphics Processing Units (GPUs) [2], and Dynamic RAMs (DRAMs) [3], respectively. However, in many real-world applications, this guardband is extremely conservative and eliminating it can result in significant power savings without any overhead. Motivated by these studies, we aim to extend the undevolting technique to commercial FPGAs. Toward this goal, we will practically demonstrate the voltage guardband for a representative Xilinx FPGA, with a preliminary concentration on on-chip memories, or Block RAMs (BRAMs).