Ring Oscillator Clocks and Margins

• Published in: 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) pp. 19 - 26
• Main Authors: Cortadella, Jordi, Lupon, Marc, Moreno, Alberto, Roca, Antoni, Sapatnekar, Sachin S.
• Format: Conference Proceeding Publication
• Language: English
• Published: IEEE 01.05.2016; Institute of Electrical and Electronics Engineers (IEEE)
• Subjects: Asynchronous circuits; Circuits asíncrons; Circuits electrònics; Clock generator; Clocks; Delay lines; Delays; EDA machinery; Enginyeria electrònica; Jitter; on-chip variability; Oscillators, Electric; Oscil·ladors elèctrics; Phase locked loops; PLL; reactive clock; Ring oscillator clocks; Ring oscillators; System-on-chip; Timing analysis; Àrees temàtiques de la UPC
• ISBN: 9781467390071; 1467390070
• DOI: 10.1109/ASYNC.2016.14

How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits.