The future of two-dimensional semiconductors beyond Moore’s law
The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thi...
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Published in | Nature nanotechnology Vol. 19; no. 7; pp. 895 - 906 |
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Main Authors | , , , , , , , , , , , , , , |
Format | Journal Article |
Language | English |
Published |
London
Nature Publishing Group UK
01.07.2024
Nature Publishing Group |
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Abstract | The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration.
This Review explores adopting 2D semiconductors to overcome the scaling bottleneck of Si-based electronics. Recent trends and potential approaches for the development of 2D materials as a channel are discussed. Following this, the prerequisites, obstacles and feasible technologies for integrating contacts and gate dielectrics with 2D semiconductor-based channels are examined. The Review also provides an industrial perspective towards facilitating monolithic 3D integration. |
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AbstractList | The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration.The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration. The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration. This Review explores adopting 2D semiconductors to overcome the scaling bottleneck of Si-based electronics. Recent trends and potential approaches for the development of 2D materials as a channel are discussed. Following this, the prerequisites, obstacles and feasible technologies for integrating contacts and gate dielectrics with 2D semiconductor-based channels are examined. The Review also provides an industrial perspective towards facilitating monolithic 3D integration. The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration. The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration.This Review explores adopting 2D semiconductors to overcome the scaling bottleneck of Si-based electronics. Recent trends and potential approaches for the development of 2D materials as a channel are discussed. Following this, the prerequisites, obstacles and feasible technologies for integrating contacts and gate dielectrics with 2D semiconductor-based channels are examined. The Review also provides an industrial perspective towards facilitating monolithic 3D integration. |
Author | Han, Ne Myo Kim, Hyunseok Lee, Sangho Kwon, Junyoung Seo, Seunghwan Lee, Eun-Kyu Kim, Jekyung Kim, Jeehwan Song, Min-Kyu Kim, Changhyun Suh, Jun Min Ryu, Huije Seol, Minsu Lee, Doyoon Kim, Ki Seok |
Author_xml | – sequence: 1 givenname: Ki Seok orcidid: 0000-0002-7958-4058 surname: Kim fullname: Kim, Ki Seok organization: Department of Mechanical Engineering, Massachusetts Institute of Technology, Research Laboratory of Electronics, Massachusetts Institute of Technology – sequence: 2 givenname: Junyoung orcidid: 0000-0002-5351-342X surname: Kwon fullname: Kwon, Junyoung organization: Samsung Advanced Institute of Technology, Samsung Electronics Co. Ltd – sequence: 3 givenname: Huije surname: Ryu fullname: Ryu, Huije organization: Samsung Advanced Institute of Technology, Samsung Electronics Co. Ltd – sequence: 4 givenname: Changhyun orcidid: 0000-0002-0989-1482 surname: Kim fullname: Kim, Changhyun organization: Samsung Advanced Institute of Technology, Samsung Electronics Co. Ltd – sequence: 5 givenname: Hyunseok orcidid: 0000-0003-3091-8413 surname: Kim fullname: Kim, Hyunseok organization: Department of Mechanical Engineering, Massachusetts Institute of Technology, Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign – sequence: 6 givenname: Eun-Kyu orcidid: 0000-0003-3056-3827 surname: Lee fullname: Lee, Eun-Kyu organization: Samsung Advanced Institute of Technology, Samsung Electronics Co. Ltd – sequence: 7 givenname: Doyoon orcidid: 0000-0003-4355-8146 surname: Lee fullname: Lee, Doyoon organization: Research Laboratory of Electronics, Massachusetts Institute of Technology, Department of Materials Science and Engineering, Massachusetts Institute of Technology – sequence: 8 givenname: Seunghwan surname: Seo fullname: Seo, Seunghwan organization: Department of Mechanical Engineering, Massachusetts Institute of Technology, Research Laboratory of Electronics, Massachusetts Institute of Technology – sequence: 9 givenname: Ne Myo orcidid: 0000-0001-9389-7141 surname: Han fullname: Han, Ne Myo organization: Department of Mechanical Engineering, Massachusetts Institute of Technology, Research Laboratory of Electronics, Massachusetts Institute of Technology – sequence: 10 givenname: Jun Min orcidid: 0000-0001-8506-0739 surname: Suh fullname: Suh, Jun Min organization: Department of Mechanical Engineering, Massachusetts Institute of Technology, Research Laboratory of Electronics, Massachusetts Institute of Technology – sequence: 11 givenname: Jekyung orcidid: 0000-0002-8250-5736 surname: Kim fullname: Kim, Jekyung organization: Department of Mechanical Engineering, Massachusetts Institute of Technology, Research Laboratory of Electronics, Massachusetts Institute of Technology – sequence: 12 givenname: Min-Kyu orcidid: 0000-0002-9233-9356 surname: Song fullname: Song, Min-Kyu organization: Department of Mechanical Engineering, Massachusetts Institute of Technology, Research Laboratory of Electronics, Massachusetts Institute of Technology – sequence: 13 givenname: Sangho orcidid: 0000-0003-4164-1827 surname: Lee fullname: Lee, Sangho organization: Department of Mechanical Engineering, Massachusetts Institute of Technology, Research Laboratory of Electronics, Massachusetts Institute of Technology – sequence: 14 givenname: Minsu orcidid: 0000-0002-8920-6181 surname: Seol fullname: Seol, Minsu email: minsu.seol@samsung.com organization: Samsung Advanced Institute of Technology, Samsung Electronics Co. Ltd – sequence: 15 givenname: Jeehwan orcidid: 0000-0002-1547-0967 surname: Kim fullname: Kim, Jeehwan email: jeehwan@mit.edu organization: Department of Mechanical Engineering, Massachusetts Institute of Technology, Research Laboratory of Electronics, Massachusetts Institute of Technology, Samsung Advanced Institute of Technology, Samsung Electronics Co. Ltd, Department of Materials Science and Engineering, Massachusetts Institute of Technology |
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SubjectTerms | 639/301/1005/1007 639/925/927/1007 Chemistry and Materials Science Dielectrics Electric contacts Electronics Electronics industry Integration Low dimensional semiconductors Materials Science Nanotechnology Nanotechnology and Microengineering Review Article Scaling Semiconductors Silicon Thickness Transistors Trends Two dimensional materials |
Title | The future of two-dimensional semiconductors beyond Moore’s law |
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