Holisitic device exploration for 7nm node

In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device...

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Bibliographic Details
Published in2015 IEEE Custom Integrated Circuits Conference (CICC) pp. 1 - 5
Main Authors Raghavan, P., Bardon, M. Garcia, Jang, D., Schuddinck, P., Yakimets, D., Ryckaert, J., Mercha, A., Horiguchi, N., Collaert, N., Mocuta, A., Mocuta, D., Tokei, Z., Verkest, D., Thean, A., Steegen, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2015
Subjects
Capacitance
design technology co-optimization (DTCO)
FinFETs
Logic gates
Metals
Performance evaluation
Power performance area (PPA)
Resistance
scaling
Stress
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Summary:In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and the design level solutions such as fin depopulation.
DOI:10.1109/CICC.2015.7338377