Complementary GaAs (CGaAs™): New enhancements

• Published in: Solid-state electronics Vol. 41; no. 10; pp. 1433 - 1439
• Main Authors: Abrokwah, J.K., Bernhardt, B., Lamacchia, M.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.10.1997
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/S0038-1101(97)00086-5

Performance improvements in complementary GaAs circuits require further device improvements. Evolutionary device improvements were made in the areas of threshold voltage, submicron gates, and gate leakage. The threshold voltage of n-channel devices were de˜coupled from p-channel devices by setting a low threshold for the NFET (0.3 V) through epitaxial design and ion implantation in the PFET active channel for reduced PFET threshold voltage. Subthreshold leakage currents were controlled for submicron and deep submicron devices through use of low temperature buffer layers and optimization of implant schedule, RTA temperature and epi/buffer contamination. As a result, 0.3 × 10 micron PFETs of good IV characteristics were realized for the first time. Transconductance was 88 mS/mm and subthreshold leakage as low as 26 nA was achieved at V ds = −1.5V·PISCES two dimensional device simulations showed optimized submicron PFETs of 0.35 micron gate lengths should yield F t of 17 GHz.