A new pointer-based instruction queue design and its power-performance evaluation

• Published in: 2005 International Conference on Computer Design pp. 647 - 653
• Main Authors: Ramirez, M.A., Cristal, A., Veidenbaum, A.V., Villa, L., Valero, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: CAM; Computer aided instruction; Instruction Wakeup; Issue Queue; Low Power; Out-of-Order Processors
• ISBN: 0769524516; 9780769524511
• ISSN: 1063-6404; 2576-6996
• DOI: 10.1109/ICCD.2005.12

Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointer-based design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, 5GHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.