A write-operation model for the FCAT-II-A 50 NS at 15 V alterable nonvolatile memory

An operational model is described for FCAT-II ( Floating Si-gate Channel Corner Avalanche Transition-II) nonvolatile memory devices or that can perform high speed write 1 and write 0 operations with 15 V pulses of less than 50 ns duration. The novel write-enable threshold phenomenon in the high-spee...

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Bibliographic Details
Published inSolid-state electronics Vol. 27; no. 10; pp. 849 - 854
Main Author Horiuchi, Masatada
Format Journal Article
LanguageEnglish
Published Elsevier Ltd 01.01.1984
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Summary:An operational model is described for FCAT-II ( Floating Si-gate Channel Corner Avalanche Transition-II) nonvolatile memory devices or that can perform high speed write 1 and write 0 operations with 15 V pulses of less than 50 ns duration. The novel write-enable threshold phenomenon in the high-speed write-1 characteristics is quantitatively analyzed by introducing an equivalent circuit model in which the resistive floating gate over the oxide steps plays an important role as a reverse-biased p- n junction. The analytical expression for the write-enable threshold, V WE , has quantitatively good agreement with experimental results.
ISSN:0038-1101
1879-2405
DOI:10.1016/0038-1101(84)90004-2