Lightweight path aggregation network for pedestrian detection on FPGA board

• Published in: Journal of parallel and distributed computing Vol. 204; p. 105137
• Main Authors: Ayachi, Riadh, Afif, Mouna, Said, Yahia, Abdelali, Abdessalem Ben
• Format: Journal Article
• Language: English
• Published: Elsevier Inc 01.10.2025
• Subjects: Advanced driver assistance systems; Convolutional neural networks; FPGA; Path aggregation network; Pedestrian detection; Pedestrian detection; Convolutional neural networks; FPGA; Advanced driver assistance systems; Path aggregation network
• ISSN: 0743-7315
• DOI: 10.1016/j.jpdc.2025.105137

•Lightweight Path Aggregation Network for pedestrian detection.•Shift the search space from mobile CPU to MPSoC devices.•Network search engine based on the multi-objective genetic algorithm (NSGA-II) with a modified strategy.•Automatic search to select the best-fit model from the generated models.•Efficiency of the proposed combination of a path aggregation framework and a mobile neural network as a backbone. In urban environments, pedestrian safety stands as a pivotal metric dictating the accuracy and efficacy of cutting-edge technologies like Advanced Driver Assistance Systems (ADAS) and autonomous vehicles. However, the deployment of such technologies introduces various constraints, notably including the computational resources of processing boards. Therefore, constructing a robust pedestrian detection system necessitates achieving a delicate balance between performance and computational complexity. In this study, we propose the development of a lightweight Convolutional Neural Network (CNN) model specifically tailored for pedestrian detection. The backbone architecture of the model was meticulously searched using a network search engine predicated on the Multi-Objective Genetic Algorithm (NSGA-II) with a customized strategy. Notably, we shifted the search space from central processing units to Multi-Processor System-on-Chip (MPSoC) devices, aligning with the practical considerations of real-world applications. Our proposed model capitalizes on the path aggregation architecture coupled with a lightweight backbone design. The core concept revolves around the efficient transfer of high semantic features from the network's bottom to its top via the shortest path, thereby enhancing detection rates without introducing undue computational complexity. To ensure compatibility with embedded devices with limited memory, the proposed model underwent compression via quantization and pruning techniques. For rigorous evaluation, we tested the pedestrian detection model on the Xilinx ZCU 102 board, utilizing the Karlsruhe Institute of Technology and Toyota Technological Institute (KITTI) dataset for training and evaluation purposes. The reported results substantiate the efficacy of our proposed model, boasting a mean average precision (mAP) of 93.6 % alongside a commendable processing speed of 13 frames per second (FPS). These outcomes underscore the suitability of the proposed model for real-life scenarios, wherein ensuring a high level of safety remains paramount.