Ultra-Low Frequency Difference Signal Multiplication Based on PLL

Ultra-low frequency difference signal is difficult to detect and process because it is easily mistaken for noise. This paper presents a method based on low-jitter PLL to detect ultra-low frequency signal. A low-jitter PLL circuit has been designed and the performance has been investigated through si...

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Bibliographic Details
Published inApplied Mechanics and Materials Vol. 599-601; no. Frontiers of Manufacturing Science and Measuring Technology IV; pp. 1797 - 1800
Main Authors Song, Kai Chen, Zhang, Man Rong, Ye, Ling Yun
Format Journal Article
LanguageEnglish
Published Zurich Trans Tech Publications Ltd 01.08.2014
Subjects
Circuit design
Jitter
Multiplication
Noise
Phase locked systems
Signal processing
Simulation
Phase Locked Loop (PLL)
Ultra-Low Frequency Difference Detection
ADS Model Simulation
Low-Jitter
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Summary:Ultra-low frequency difference signal is difficult to detect and process because it is easily mistaken for noise. This paper presents a method based on low-jitter PLL to detect ultra-low frequency signal. A low-jitter PLL circuit has been designed and the performance has been investigated through simulation. The jitter is as low as 10-12s. The optimized low-jitter PLL can be used for the multiplication of ultra-low frequency difference and improve the measurement accuracy substantially.
Bibliography:Selected, peer reviewed papers from the 2014 4th International Conference on Frontiers of Manufacturing Science and Measuring Technology (ICFMM 2014), June 19-20, 2014, Guilin, China
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SourceType-Scholarly Journals-1
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ISBN:303835192X
9783038351924
ISSN:1660-9336
1662-7482
1662-7482
DOI:10.4028/www.scientific.net/AMM.599-601.1797