Hierarchical compilation of macro dataflow graphs for multiprocessors with local memory

This paper presents a hierarchical approach for compiling macro dataflow graphs for multiprocessors with local memory. Macro dataflow graphs comprise several nodes (or macro operations) that must be executed subject to prespecified precedence constraints. Programs consisting of multiple nested loops...

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Bibliographic Details
Published inIEEE transactions on parallel and distributed systems Vol. 5; no. 7; pp. 720 - 736
Main Authors Srinivasa Prasanna, G.N., Agarwal, A., Musicus, B.R.
Format Journal Article
LanguageEnglish
Published Los Alamitos, CA IEEE 01.07.1994
IEEE Computer Society
Subjects
Applied sciences
Computational modeling
Computer science; control theory; systems
Concurrent computing
Distributed computing
Exact sciences and technology
Laboratories
Parallel processing
Phase estimation
Processor scheduling
Prototypes
Resource management
Runtime
Software
Software engineering
Multiprocessor
Compiler
Compilation
Parallel processing
Scheduling
Localization
Parallelization
Communication
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ISSN1045-9219
DOI10.1109/71.296318

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Summary:This paper presents a hierarchical approach for compiling macro dataflow graphs for multiprocessors with local memory. Macro dataflow graphs comprise several nodes (or macro operations) that must be executed subject to prespecified precedence constraints. Programs consisting of multiple nested loops, where the precedence constraints between the loops are known, can be viewed as macro dataflow graphs. The hierarchical compilation approach comprises a processor allocation phase followed by a partitioning phase. In the processor allocation phase, using estimated speedup functions for the macro nodes, computationally efficient techniques establish the sequencing and parallelism of macro operations for close-to-optimal run-times. The second phase partitions the computations in each macro node to maximize communication locality for the level of parallelism determined by the processor allocation phase. The same approach can also be used for programs consisting of multiple loop nests, when each of the nested loops can be characterized by a speedup function. These ideas have been implemented in a prototype structure-driven compiler, SDC, for expressions of matrix operations. The paper presents the performance of the compiler for several matrix expressions on a simulator of the Alewife multiprocessor.< >
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ISSN:1045-9219
DOI:10.1109/71.296318