CONNA: Configurable Matrix Multiplication Engine for Neural Network Acceleration

• Published in: Electronics (Basel) Vol. 11; no. 15; p. 2373
• Main Authors: Park, Sang-Soo, Chung, Ki-Seok
• Format: Journal Article
• Language: English
• Published: Basel MDPI AG 01.08.2022
• Subjects: Acceleration; Accelerators; Arrays; Artificial neural networks; Classification; Computer vision; Energy efficiency; Frames per second; Hardware; Matrices (mathematics); Natural language processing; Neural networks; Power consumption; Power management; RISC; Speech recognition
• ISSN: 2079-9292; 2079-9292
• DOI: 10.3390/electronics11152373

Convolutional neural networks (CNNs) have demonstrated promising results in various applications such as computer vision, speech recognition, and natural language processing. One of the key computations in many CNN applications is matrix multiplication, which accounts for a significant portion of computation. Therefore, hardware accelerators to effectively speed up the computation of matrix multiplication have been proposed, and several studies have attempted to design hardware accelerators to perform better matrix multiplications in terms of both speed and power consumption. Typically, accelerators with either a two-dimensional (2D) systolic array structure or a single instruction multiple data (SIMD) architecture are effective only when the input matrix has shapes that are close to or similar to a square. However, several CNN applications require multiplications of non-squared matrices with various shapes and dimensions, and such irregular shapes lead to poor utilization efficiency of the processing elements (PEs). This study proposes a configurable engine for neural network acceleration, called CONNA, whose computation engine can conduct matrix multiplications with highly utilized computing units, regardless of the access patterns, shapes, and dimensions of the input matrices by changing the shape of matrix multiplication conducted in the physical array. To verify the functionality of the CONNA accelerator, we implemented CONNA as an SoC platform that integrates a RISC-V MCU with CONNA on Xilinx VC707 FPGA. SqueezeNet on CONNA achieved an inference performance of 100 frames per second (FPS) with 2.36 mm2 and 83.55 mW in a 65 nm process, improving efficiency by up to 34.1 times better than existing accelerators in terms of FPS, silicon area, and power consumption.