Design of a reconfigurable network-on-chip for next generation FPGAs using Dynamic Partial Reconfiguration

• Published in: Microelectronics Vol. 108; p. 104964
• Main Authors: Ahmed, Ramy, Mostafa, Hassan, Khalil, A.H.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.02.2021
• Subjects: Dynamic partial reconfiguration; Field programmable gate arrays; Network on chip; Dynamic partial reconfiguration; Network on chip; Field programmable gate arrays
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2020.104964

Introducing the reconfigurability concept into one of the most ramping and trending design platforms like the NoC is considered a good opportunity for gaining the most out of them. The high flexibility and full customization of the reconfigurable NoC could open the door for a completely adaptive NoC that suits a large number of benchmarks according to runtime needs and requirements. The main objective of this work is to present the Dynamic Partial Reconfiguration (DPR) support to CONNECT Network-on-Chip (NoC) for Field Programmable Gate Array (FPGA) applications. It also analyzes the effect of this reconfigurability on the performance of the network and how reconfigurability could lead to area and power saving. Reconfigurability during runtime leads to more flexible NoCs and enables full customization for dynamic reconfigurable applications. In comparison with static NoCs, dynamically reconfigurable NoCs achieve more area utilization by reusing a part of the network area resources when it is not required during runtime. A reconfiguration tool is developed helping the designer to decide the optimal network structure for every application used. The reconfiguration tool requires as inputs the minimum needed throughput and the expected traffic load. Those inputs are used to decide the best network configuration and the minimum area that achieves those requirements.