Junctionless versus inversion-mode lateral semiconductor nanowire transistors

This paper reports on gate-all-around silicon nanowire field-effect transistors (FETs) built in a lateral configuration, which represent the ultimate scaling limit of triple-gate finFET devices and allow a less disruptive CMOS scaling path in terms of processing and circuit layout design. We address...

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Bibliographic Details
Published inJournal of physics. Condensed matter Vol. 30; no. 38; p. 384002
Main Authors Veloso, A, Matagne, P, Simoen, E, Kaczer, B, Eneman, G, Mertens, H, Yakimets, D, Parvais, B, Mocuta, D
Format Journal Article
LanguageEnglish
Published England IOP Publishing 26.09.2018
Subjects
CMOS scaling
DC and analog/RF performance
junctionless and inversion-mode type of transistors
nanowire FETs
noise
reliability
variability
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Summary:This paper reports on gate-all-around silicon nanowire field-effect transistors (FETs) built in a lateral configuration, which represent the ultimate scaling limit of triple-gate finFET devices and allow a less disruptive CMOS scaling path in terms of processing and circuit layout design. We address several of their critical technological challenges, looking in particular at doping strategies. A comprehensive review of junctionless versus inversion-mode type of transistors is here presented, evaluating the impact on the devices' operation mode and on device properties such as: variability, reliability, noise, DC and analog/RF performance. We also discuss the potential for further manufacturable co-integration options.
Bibliography:JPCM-111203.R1
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ISSN:0953-8984
1361-648X
DOI:10.1088/1361-648X/aad7c7